Upon completion of wafer fabrication steps forming the many integrated circuit dies on a wafer, the wafer proceeds to an intermediate testing stage while still in wafer form. This intermediate testing stage is commonly known as the DC parametric testing stage. It is referred to herein as the wafer level testing stage or simply the wafer level stage and includes two phases or steps of DC wafer level testing. First, selected test patterns formed at dedicated sites on the wafer are tested by a test pattern tester to check device parametrics indicating process variation. Second, each die on the wafer is tested on a DC parametric tester using a wafer probe for wafer sorting.
Typically, each wafer is formed with one or more process monitor test dies distributed across the wafer. The test dies are formed with DC test patterns for representative testing of selected DC parameters at the wafer level stage. The DC test patterns and DC parametric tests performed by the test pattern tester on the test patterns are designed to detect longer term changes in the IC wafer fabrication process for purposes of process control.
DC parametric testing is then performed on the individual dies of the wafer using a DC parametric tester. Physical contact is made with the bond pads of the respective dies using an automated wafer probe which steps from one die to another. The DC parameter tester forces DC currents and voltages for measuring DC parameters such as voltage thresholds, power rail voltages, and other voltages and currents of the respective IC component devices. Conventional DC parameter testers and wafer probes are generally limited to DC testing. The high impedance and high capacitance characteristic of the wafer probe make it impractical for testing AC parameters and high frequency characteristics. AC parameter testing is performed after cutting the wafer and packaging of individual dies or chips. However some limited low frequency AC testing has been conducted at the wafer level stage as described by Richard B. Merrill et al. in U.S. Pat. No. 5,039,602 on Aug. 13, 1991 for METHOD OF SCREENING AC PERFORMANCE CHARACTERISTICS DURING DC PARAMETRIC TEST OPERATION.
During the second phase of DC parameter testing, IC dies of the wafer that fail to meet specified DC parameter characteristics are marked for rejection, a step referred to as wafer sorting or "wafer sort". Following the "wafer sort", the wafer is shipped for scribing into individual integrated circuit dies and packaging of the acceptable chips. After packaging the integrated circuit devices then undergo more sophisticated AC parametric testing and dynamic AC function testing in integrated circuit device testers such as the Micro Component Technology, Inc. MCT 2000 Series Test System. Further description of AC parametric testing is found in the William H. Morong U.S. Pat. No. 5,101,153 issued Mar. 31, 1992 for PIN ELECTRONICS TEST CIRCUIT FOR IC DEVICE TESTING.
At the stage of AC parametric testing of individual packaged IC devices, a further percentage of the now packaged dies or chips are rejected. The objective of the manufacturing process is to maximize yield after the expense of scribing and packaging the individual dies of the wafer. A troublesome low yield of packaged dies occurs where the customer product specifications and acceptable range of performance of a selected sensitive AC parameter of an IC product may be substantially narrower than the general range of variation of the selected sensitive AC parameter produced by the IC fabrication process on line at the time of production. In that event, the yield may be particularly low with a high percentage of rejection of already packaged chips which fail the more sophisticated AC parametric tests and dynamic AC function tests.
By way of example, the cost of production of integrated circuit dies formed on a wafer at the wafer level sorting stage before scribing and packaging may be, for example in the range of ten cents per die. On the other hand, after scribing and packaging the cost per packaged IC device may be for example thirty cents per packaged die or chip. Low yield at the stage of AC parametric testing therefore disproportionately increases manufacturing cost of the acceptable packaged chips. Packaged IC device yield from AC parametric testing may therefore be unacceptably low and manufacturing costs excessive when customer product specifications for performance variation in a selected sensitive AC parameter are substantially narrower than the range of variation in the sensitive AC parameter generally produced by the on line wafer fabrication process.